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1 lt4220 4220f applicatio s u features descriptio u typical applicatio u dual supply hot swap controller n hot swap tm controller for positive and negative supplies n supply tracking mode n 2.7v to 16.5v operation n analog current limit with foldback n allows safe board insertion and removal from a live backplane n open-collector power good comparators n automatic retry or latchoff after a current fault n dual undervoltage lockout comparator inputs n current fault indication n live board insertion n raid systems n C5.2v ecl supplies n industrial controls n split supply systems , ltc and lt are registered trademarks of linear technology corporation. the lt ? 4220 16-pin dual voltage hot swap controller allows a board to be safely inserted and removed from a live backplane. the device operates with any combination of 2.7v to 16.5v and C2.7v to C16.5v supplies. using two external n-channel pass transistors, the board supply voltages can be ramped up at an adjustable rate. a select- able tracking mode allows dual supply tracking control for ramping the positive and negative supplies together. the lt4220 features foldback current limit and latches off both gates if either supply remains in current limit longer than an adjustable time amount. the ic can be configured for automatic restart after a delay set by the same timer. a power good signal indicates when the output voltages monitored by the two fb comparators are within tolerance, and the gate drive signals are at their full on voltage. the lt4220 is available in a 16-lead narrow ssop package. hot swap is a trademark of linear technology corporation. v cc on + c6 1 f c5 1 f r2 4.99k r1 36.5k r4 4.99k r3 36.5k ?2v v ee 12v v cc fault timer gnd track on pwrgd fb + r10 4.99k r9 36.5k 12v v out + r12 4.99k r11 36.5k 4220 ta01 ?2v v out r7 10 fb sense + r s + 0.005 r s 0.005 gate + r6 1k r5 10 c1 10nf r8 1k c2 10nf c3 100nf q1 sub85n03-04 v ee sense sensek lt4220 gate q2 sub85n03-04 cl2 cl1 z2* r14 10 connector 1 connector 2 c4 100nf z1* r13 10 v in + v in * 1sma13at3 transient voltage suppressor + + 716 15 14 12 34 12 11 6 8 9 10 13 5 r15 20k r16, 20k c7 10nf c8 10nf d1 in4001 d2 in4001 12v 10a hot swap controller 12v v in + 12v v out + ?2v v in ?2v v out time (10ms/div)
2 lt4220 4220f symbol parameter conditions min typ max units v cc v cc operating range l 2.7 16.5 v i cc v cc supply current l 2.7 4 ma v ee v ee operating range l C2.7 C16.5 v i ee v ee supply current C1.6 C2.4 ma v plko v cc undervoltage lockout l 2.35 2.45 2.55 v v mlko v ee undervoltage lockout l C2.4 C2.45 C2.5 v v on + h on + on threshold on + rising l 1.22 1.24 1.26 v v on + hys on + hysteresis l 25 50 70 mv d v on + h on + on threshold line regulation v cc = 2.7v, v ee = C2.7v to v cc = 16.5v, v ee = C16.5v l 0.02 0.15 mv/v d v on C h on C on threshold line regulation v cc = 2.7v, v ee = C2.7v to v cc = 16.5v, v ee = C16.5v l 0.05 1 mv/v v on C hys on C hysteresis l 25 50 70 mv v on C h on C on voltage threshold on C falling l C1.22 C1.24 C1.26 v i on + on + input current v on + = 2v l 0.01 1 m a i on C on C input current v on C = gnd l 0.01 1 m a v fb + h fb + pwrgd voltage threshold fb + rising l 1.22 1.24 1.26 v v fb + hys fb + hysteresis gate = 5v l 25 50 70 mv v fb C h fb C pwrgd voltage threshold fb C falling l C1.22 C1.24 C1.26 v v fb C hys fb C hysteresis gate = 3v l 25 50 70 mv (notes 1, 2) v cc to gnd ............................................................. 22v v ee to gnd ........................................................... C22v track, timer .............................. C 0.3v to v cc + 0.3v on + , fb + ................................. v ee C 0.3v to v cc + 0.3v on C , fb C .................................. v ee C 0.3v to v cc + 0.3v gate + ................................................ C0.3v to v cc + 8v gate C .............................. C16.5v with v ee = C22v to 0v sense + ............................................. C0.3v to v cc + 5v sense C , sensek ....................... v ee C 0.3v to v ee + 3v pwrgd, fault ................................. C0.3v to v cc + 5v operating temperature range lt4220c ........................................... 0 c t a 70 c lt4220i ....................................... C40 c t a 85 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c absolute m axi m u m ratings w ww u package/order i n for m atio n w u u order part number lt4220cgn lt4220ign gn part marking 4220 4220i t jmax = 125 c, q ja = 130 c/w the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc = 5v, v ee = C5v, unless otherwise noted. consult ltc marketing for parts specified with wider operating temperature ranges. gn package 16-lead plastic ssop 1 2 3 4 5 6 7 8 top view 16 15 14 13 12 11 10 9 v ee sensek sense gate fb on track timer v cc sense + gate + fb + on + fault pwrgd gnd dc electrical characteristics
3 lt4220 4220f symbol parameter conditions min typ max units i infb + fb + input current fb + = 3v l 0.09 1 m a i infb C fb C input current fb C = C3v l 0.08 1 m a d v fb + h fb + pwrgd threshold line regulation v cc = 2.7v, v ee = C2.7v to v cc = 16.5v, v ee = C16.5v l 0.015 0.15 mv/v d vfb C h fb C pwrgd threshold line regulation v cc = 2.7v, v ee = C2.7v to v cc = 16.5v, v ee = C16.5v l 0.05 0.5 mv/v v sense + sense + trip voltage (v cc C v sense + )v fb + = 0v, gate + C 0.5v l 61522 mv v fb + = 1v, gate + C 0.5v 36 48 60 mv v sense C sense C trip voltage (v sensek C v sense C )v fb C = 0v, gate C C 0.5v l C10 C15 C22 mv v fb C = C1v, gate C C 0.5v C43 C52 C61 mv i gateup + gate + pull-up current charge pump on, v gate + = 7v l C9 C13 C17 m a i gateup C gate C pull-up current v gate C = C3v l C6 C10 C14 m a i gatedn + gate + pull-down current any fault condition, v gate + = 1v l 20 40 60 ma i gatedn C gate C pull-down current any fault condition, v gate C = v ee + 4v l 30 70 130 ma d v gate + external n-channel gate + drive v gate + C v cc , v cc = 2.7v, v ee = C2.7v l 3.5 4 6 v v cc = 5v to 16.5v, v ee = C5v to C16.5v 5 6.5 8 v d v gate C external n-channel gate C drive v gate C C v ee , v cc = 2.7v, v ee = C2.7v l 3.5 5.2 6 v v cc = 5v to 16.5v, v ee = C5v to C16.5v 7.5 8.5 9 v v timerh timer high threshold, sets fault l 1.22 1.24 1.26 v v timerl timer low threshold, allows restart l 0.4 0.5 0.6 v i timerup timer pull-up current timer = 0v l C40 C65 C85 m a i timerdn timer pull-down current timer = 1v l 2 3.3 4.5 m a i timer(r) timer current ratio i timerdn /i timerup 57 % v ol pwrgd output low voltage i o = 2ma l 0.3 v i o = 5ma 0.5 v i oh pwrgd leakage current v pwrgd = 16.5v l 0.1 2 m a v fol fault output low voltage i o = 2ma l 0.3 v i o = 5ma 0.5 v i fph fault leakage current v fault = 16.5v l 0.06 2 m a v trkthr track input threshold l 0.3 0.8 1.1 v i trk track input current track = 16.5v l 0.05 2 m a v trkfb + track mode fb + threshold i gate + = 0 m a, track = v cc (note 3) l 40 70 mv v trkfb C track mode fb C threshold i gate C = 0 m a, track = v cc (note 3) l 40 80 mv dc electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc = 5v, v ee = C5v, unless otherwise noted.
4 lt4220 4220f the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc = 5v, v ee = C5v, unless otherwise noted. ac electrical characteristics typical perfor a ce characteristics uw supply voltage (v) 0 supply current (ma) 2 3 20 4220 g01 1 0 5 10 15 4 fb + voltage (v) ?.5 v cc -sense + voltage (mv) 50 40 30 20 10 0 ?.0 0.5 0 0.5 4220 g02 1.0 1.5 ?.5 ?.0 0.5 0 0.5 1.0 1.5 fb voltage (v) sensek-sense ? voltage (mv) 60 50 40 30 20 10 0 4220 g03 t a = 25 c i cc i ee v cc = 5v v ee = ?v on + = 2v on = ?v t a = 25 c v cc = 5v v ee = ?v on + = 2v on = ?v t a = 25 c positive circuit breaker sense voltage vs fb + voltage negative circuit breaker sense voltage vs fb C voltage supply current vs supply voltage symbol parameter conditions min typ max units t phlon + on + low to gate + low 5k pull-up to gate + , 1nf load capacitor l 0.6 0.8 1.2 m s t plhon + on + high to gate + high 5k pull-up to gate + , 1nf load capacitor l 0.6 1.5 3 m s t phlfb + fb + low to pwrgd low 5k pull-up to pwrgd l 0.5 0.8 1.2 m s t plhfb + fb + high to pwrgd high 5k pull-up to pwrgd l 0.6 1.25 3 m s t phlon C on C low to gate C low 5k pull-up to gate C , 1nf load capacitor l 0.6 1 1.5 m s t plhon C on C high to gate C high 5k pull-up to gate C , 1nf load capacitor l 1 2.1 3.5 m s t phlfb C fb C low to pwrgd low 5k pull-up to pwrgd l 0.6 1 1.5 m s t plhfb C fb C high to pwrgd high 5k pull-up to pwrgd l 0.8 1.25 2 m s t sense + sense + to gate + low 1nf on gate + , 100mv step, 5k pull-up l 146 m s t sense C sense C to gate C low 1nf on gate C , 100mv step, 5k pull-up l 146 m s note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: all currents into device pins are positive; all currents out of device pins are negative. all voltages referenced to ground (gnd) unless specified. note 3: the absolute voltage difference between fb + and fb C required to force either the gate + or gate C current to 0 m a.
5 lt4220 4220f gate + pull-down current vs gate + voltage typical perfor a ce characteristics uw gate + drive vs v cc v cc (v) 3 069121518 8 7 6 5 4 4220 g04 gate + drive (v gate + ?v cc ) (v) v ee = ?v v ee = ?.7v t a = 25 c v cc (v) 3 069121518 75 70 65 60 55 50 4220 g11 timer pull-up current ( a) t a = 25 c v ee (v) 3 069121518 10 9 8 7 6 5 4 4220 g05 gate drive (v gate ?v ee ) (v) v cc = 5v t a = 25 c gate + voltage (v gate + ?v cc ) (v) 0 gate + pull-up current ( a) 6 4220 g06 24 16 14 12 10 8 6 4 2 0 1357 gate + voltage (v) 0 gate + pull-down current (ma) 12 4220 g07 48 60 50 40 30 20 10 0 900 800 700 600 500 400 300 200 100 0 2 6 10 14 gate voltage (v gate ?v ee ) (v) 0 gate pull-down current (ma) 7 4220 g09 24 70 60 50 40 30 20 10 0 1 36 58 v cc = 5v v ee = ?v on = 0v fb = ?v t a = 25 c gate voltage (v gate ?v ee ) (v) 0 gate pull-up current ( a) 4220 g08 48 12 10 8 6 4 2 0 210 6 v cc = 5v v ee = ?v sense + = v cc sense = v ee t a = 25 c v ol (mv) sink current (ma) 4220 g10 02 4 6810 v cc = 5v v ee = ?v t a = 25 c pwrgd fault temperature ( c) ?0 45.0 44.5 44.0 43.5 43.0 42.5 42.0 41.5 41.0 20 60 4220 g12 ?0 0 40 80 hysteresis voltage (mv) v cc = 5v v ee = ?v v sense + = v cc v sense = v ee t a = 25 c v cc = 5v v ee = ?v on + = 0v fb + = 2v t a = 25 c v cc = 2.7v pwrgd and fault v ol vs sink current gate C pull-up current vs gate C voltage gate + pull-up current vs gate + voltage gate C drive vs v ee gate C pull-down current vs gate C voltage timer pull-up current vs v cc on + , on C and fb + , fb C hysteresis vs temperature
6 lt4220 4220f typical perfor a ce characteristics uw fb + and on + threshold voltage vs temperature temperature ( c) ?0 1.241 1.240 1.239 1.238 1.237 1.236 1.235 20 60 4220 g13 ?0 0 40 80 ?0 20 60 ?0 0 40 80 ?0 20 60 ?0 0 40 80 ?0 20 60 ?0 0 40 80 threshold voltage (v) temperature ( c) ?.241 ?.240 ?.239 ?.238 ?.237 ?.236 ?.235 4220 g14 threshold voltage (v) temperature ( c) 70 69 68 67 66 65 64 4220 g15 timer pull-up current ( a) temperature ( c) 15 14 13 12 11 10 4220 g16 gate + , gate pull-up current ( a) gate + gate fb C and on C threshold voltage vs temperature timer pull-up current vs temperature gate + , gate C pull-up current vs temperature
7 lt4220 4220f uu u pi fu ctio s v ee (pin 1): negative supply. the negative supply input ranges from C2.7v to C16.5v for normal operation. i ee is typically C1.6ma. an internal undervoltage lockout circuit disables the device for inputs greater than C2.45v. a 10 w , 1 m f rc bypass network from v in C to the v ee pin decouples transients from the device. sensek (pin 2): negative supply current limit kelvin sense pin. connect to v in C . sense C (pin 3): negative supply current limit sense pin. a sense resistor is placed in the supply path between sensek and sense C . the current limit circuit will regulate the voltage across the sense resistor to C50mv (sensek C sense C ) when the fb C voltage is less than C0.7v. if v fb C goes above C0.7v, the voltage across the sense resistor decreases linearly and stops at C15mv when v fb C is 0v. if current limit is not used, connect to sensek. gate C (pin 4): gate drive for the external negative supply n-channel fet. an internal 10 m a current source drives the pin. an external capacitor connected from the gate C pin to v out C will control the rising slope of the v out C signal. the voltage is clamped to 9v above v ee . when the current limit is reached, the gate C pin voltage will be adjusted to maintain a constant voltage across the r s C resistor while the timer capacitor starts to charge. if the timer pin voltage exceeds 1.24v, the fault latch will be set and both gate C and gate + pins will be pulled low. the gate C pin is pulled to v ee whenever the on + pin is below 1.24v, the on C pin is above C1.24v, or either supply is in the undervoltage lockout voltage range, or the fault latch is set by the timer pin rising above 1.24v. fb C (pin 5): negative power good comparator input. this pin monitors the negative output voltage (v out C ) with an external resistive divider. when the voltage on fb C is below C1.24v and the initial gate C drive voltage has reached a maximum (indicated by setting the internal gate C good latch) and the fb + release conditions are met, the pwrgd pin is released. pwrgd is pulled low when the fb C pin is above C1.185v. note the pwrgd pin is wire- ored with the fb + pin conditions. fb C also controls the negative supply current limit sense amplifier input offset to provide foldback current limit. the fb C pin linearly reduces the negative supply sense ampli- fier offset from C52mv to C15mv for fb C in the range C0.75v < fb C < 0v. to disable v ee pwrgd and foldback current limit, the fb C pin should be set to a voltage in the range: C1.3v > fb C > v ee + 0.5v but should never be more negative then C5.8v for normal operation. on C (pin 6): the negative supply good comparator input. this pin monitors the negative input voltage (v ee ) with an external resistive divider for undervoltage lockout. when the voltage at the on C pin is below the v on C h high-to-low threshold (C1.24v), the negative supply is considered good. if the on C pin rises above C1.185v, both gate C and gate + are pulled low. if on C is not used, the on C pin should be set to C1.3v > on C > v ee + 0.5v. track (pin 7): supply tracking mode control. if the track pin is pulled high, the internal supply tracking circuit will be enabled during start-up. the track circuit monitors the fb + and the fb C pins to keep their magnitude within a small voltage range by controlling the gate + and gate C charge currents. the tracking is disabled when either fb comparator indicates the output is good. tracking is re- enabled if on + is pulled below 1.185v, on C is pulled above C1.185v or either supply is below the internal undervoltage lockout. typically, the track pin is tied to gnd or to v cc . if left floating, tracking is enabled. timer (pin 8): fault time out control. an external timing capacitor at this pin programs the maximum time the part is allowed to remain in current limit before issuing a fault and turning off the external fets. additionally, for autorestart, this pin controls the time before an autorestart is initiated. when the part goes into current limit, a 65 m a pull-up current source starts to charge the timing capacitor. when the voltage reaches v timerh (1.24v), the internal fault latch is set, fault pulls low and both gate pins are pulled low; the pull-up current will be turned off and the capacitor is discharged by a 3.3 m a pull-down current. when the timer pin falls below 0.5v, the part is allowed to restart if the on + pin is pulsed below 1.185v, thereby resetting internal fault latchtypically done by connecting the
8 lt4220 4220f uu u pi fu ctio s fault pin to the on + pin, otherwise the part remains latched off. to disable the timeout circuit breaker, connect the timer pin to gnd. gnd (pin 9): supply ground pin. pwrgd (pin 10): open-collector output to gnd. pwrgd goes to high impedance after the initial gate C and final gate + pins have reached their maximum voltage and after the fb + pin goes above 1.24v low-to-high threshold and after the fb C pin falls below C1.24v high-to-low threshold. an external pull-up resistor can pull the pin to a voltage higher or lower than v cc . if not used, pwrgd can be left floating or tied to gnd. fault (pin 11): open-collector output to gnd. the fault pin is pulled low whenever the timer pin rises above v timerh (1.24v) threshold, thereby setting the internal fault latch. it goes to high impedance whenever the internal fault latch is reset. the fault latch is reset with either internal undervoltage lockout conditions, or by the on comparators if the timer pin is also below 0.5v. if not used, the fault pin can be left floating or tied to gnd. on + (pin 12): positive supply good comparator input. it monitors the positive input voltage (v cc ) with an external resistive divider for undervoltage lockout. when the volt- age on on + is above the v on + h high-to-low threshold (1.24v) the positive supply is considered good. if on + drops below 1.185v, both gate C and gate + are pulled low. if on + is pulled low after a current limit fault and when the timer pin is below 0.5v, the fault latch is reset allowing the part to turn back on. typically the fault pin is tied back to the on + pin for autorestart. if not used, the on + pin should be set to a voltage in the range of 1.3v < on + < v cc + 0.3v. the on + pin requires a bypass capacitor connected to ground. fb + (pin 13): positive power good comparator input. this pin monitors the positive output voltage (v out + ) with an external resistor divider. when the voltage on fb + is above the v fb + h low-to-high threshold (1.24v) and the gate + drive voltage has reached a maximum, the pwrgd is released. pwrgd is pulled low when the fb + pin is below 1.185v. the pwrgd pin is wire-ored with the fb C pin conditions. fb + also controls the positive current limit sense amplifier input offset to provide foldback current limit. the fb + pin linearly reduces the positive sense amplifier offset from 48mv to 15mv for fb + in the range 0.85v > fb + > 0v. if pwrgd and foldback current limit are not used, the fb + pin should be set to a voltage in the range of 1.3v < fb + < v cc + 0.3v. gate + (pin 14): high side gate drive for the external positive supply n-channel fet. an internal charge pump guarantees at least 3.5v above v cc , for supply voltages at 2.7v increasing to a minimum of 5v above v cc for supply voltages greater than 5v. a 10 m a pull-up current source drives the pin. an external capacitor connected from the gate + pin to gnd will control the rising slope of the gate + signal. the voltage is clamped to 7v above v cc . when the current limit is reached, the gate + pin voltage will be adjusted to maintain a constant voltage across the r s + resistor while the timer capacitor starts to charge. if the timer pin voltage exceeds 1.24v, the gate + pin will be pulled low. the gate + pin is pulled to gnd whenever the on + pin is below 1.24v, the on C pin is above C1.24v, either supply is in the undervoltage lockout voltage range, or the timer pin rises above 1.24v. sense + (pin 15): positive supply current limit sense pin. a sense resistor must be placed in the supply path be- tween v cc and sense + . the current limit circuit will regulate the voltage across the sense resistor to 50mv (v cc C sense + ) when the fb + voltage is greater than 0.85v. if v fb + goes below 0.85v, the voltage across the sense resistor decreases linearly and stops at 15mv when v fb + is 0v. v cc (pin 16): positive supply. the positive supply input ranges from 2.7v to 16.5v for normal operation. i cc is typically 2.7ma. an internal undervoltage lockout circuit disables the chip for inputs less than 2.45v. place a 0.1 m f bypass capacitor next to the v cc pin.
9 lt4220 4220f block diagra w + 13 + 1.24v + ?.24v uvlo v cc and v ee good fb + 6 on + + + + 1.24v 0.5v 1.24v 12 on + fb 1.24v p gate good n gate good 5 track 7 v ee v cc v cc 1 gnd 9 16 s r q s r q s r q q q q s r r q q 10 pwrgd gate good latches track off latch toff gate on v cc v cc fault fault latch timer and logic 11 fault gate + 15 sense + pump i lim v cc 3 a 10 a 10 a on on en track fb + 60 a current limit from sense amps
10 lt4220 4220f ti i g diagra s w u w on + 4220 f01 gate + 0.5v t plhon + 1v 1v 0v 0v 10v t phlon + 100mv figure 1. on + -to-gate + timing figure 2. fb + -to-pwrgd timing fb + 4220 f02 pwrgd 2.5v t plhfb + 1v 1v 2.5v t phlfb + 0v 0v 100mv on 0v v ee 4220 f03 gate v ee + 1.2v ?v v ee + 3.5v ?v t phlon t plhon fb 4220 f04 pwrgd 2.5v ?v 2.5v ?v t phlfb t plhfb 0v 0v figure 3. on C -to-gate C timing figure 4. fb C -to-pwrgd timing v cc ?sense + 4220 f05 gate + 10v t sense + 100mv 50mv 0v 0v v ee ?sense 0v 4220 f06 gate ?v v ee t sense ?00mv ?0mv figure 5. sense + -to-gate + timing figure 6. sense C -to-gate C timing hot circuit insertion when circuit boards are inserted into a live backplane, the circuit board bypass capacitors can draw large peak currents from the backplane power bus as they charge up. the lt4220 is designed to turn on a boards v dual supplies in a controlled manner, allowing the circuit board to be safely inserted or removed from a live backplane. the part provides supply tracking as well as undervoltage and overcurrent protection. power good and fault output sig- nals indicate, respectively, if both power output voltages are ready or if an overcurrent time-out fault has occurred. applicatio s i for atio wu uu the dual power supply on the circuit board is controlled with two external n-channel pass transistors q1 and q2 in the v dual power supply path. the sense resistors r s + and r s C provide current detection while capacitor c1 and c2 control the v out + and v out C slew rate. optionally, the track pin can be tied to v cc enabling the dual output voltages to ramp up together by tracking the voltages at the fb + and fb C pins. resistors r6 and r8 provide current control loop compensation while r5 and r7 prevent high frequency oscillations in q1 and q2. c3 and r8 on q2 prevent fast dv/dt transients from turning q2 on during
11 lt4220 4220f initial power-up sequence after the power pins first make contact, transistors q1 and q2 remain off. if the voltage at the on + and on C pins exceed the turn-on threshold voltage, the internal voltage on the v cc and v ee power pins exceed the undervoltage lockout threshold, and the timer pin voltage is less than 1.24v, the gate drive to transistors q1 and q2 will be turned on. the voltage on the gate + and gate C pins will be regulated to control the inrush current if the voltage across r s + or r s C exceeds the sense amplifier current limit threshold. if supply tracking is enabled, each gate will also be regulated to keep the magnitudes at the fb + and fb C pins within 50mv of each other. v cc on + c6 1 f c5 1 f r2 r1 r4 r3 v ee v cc fault timer gnd on pwrgd fb + r10 r9 v out + r12 r11 4220 f07 v out r7 10 fb sense + r s + r s gate + r6 1k r5 10 c1 10nf r8 1k c2 10nf c3 100nf q1 v ee sense sensek lt4220 gate q2 cl2 cl1 z2* r14 10 c4 100nf z1* r13 10 connect for auto restart backplane connector staggered pcb edge connector v in + v in gnd must connect first gnd *transient voltage suppressor esd control track 7 10 13 5 4 3 2 1 6 9 8 11 12 16 15 14 r16, 20k c7 c8 + + d1 in4001 d2 in4001 figure 7. hot swap controller on daughter board with tracking disabled applicatio s i for atio wu uu live insertion. resistive dividers r1, r2 and r3, r4 pro- vide undervoltage sensing. resistor dividers r9, r10 and r11, r12 provide a power good signal and control output voltage tracking when track is enabled. internal supply diodes the lt4220 contains two internal diodes which clamp v ee and v cc with respect to gnd in the event either supply pin is floating. v ee is clamped one diode above gnd and v cc is clamped one diode below gnd. the current through these diodes are designed to handle 10ma internal device current and should not be used for high load current conditions.
12 lt4220 4220f applicatio s i for atio wu uu whenever the output voltages reach their final value as sensed by r9, r10 and r11, r12 and both gate signals are fully on, the pwrgd pin will go high impedance. a typical timing sequence is shown in figure 8 with tracking enabled. the sequence is as follows: 1) the power pins make contact and the undervoltage lockout thresholds are exceeded. 2) the on comparator thresholds are exceeded and the gate pins start ramping up. v out + follows gate + by the n-channel fet threshold voltage. 3) gate + is limited by the tracking circuit because v out C lags behind v out + . when v out C starts ramping, gate C holds at approximately the threshold voltage of the n-channel fet due to c2 slew rate control. 4) when the magnitude of v out C catches up with v out + , gate + resumes ramping. the slowest v out will limit the faster v out slew rate. 5) gate + internal gate good signal threshold is reached. 6) gate C internal gate good signal threshold is reached, enabling the fb output comparators. if both fb com- parators indicate the output is good, the pwrgd pin output goes high impedance and is pulled up by an external pullup resistor. power supply ramping for large capacitive loads, the inrush current will be limited by the v out + and v out C slew rate or by the fold-back current limit. for a desired inrush current that is less than the fold-back current limit, the feedback networks r6, c1 and r8, c2 can be used to control the v out slew rate. for the desired inrush current and typical gate pull-up current, the feedback network capacitors c1 and c2 can be calcu- lated as: c1 = (10 m a ? cl1)/i inrush + and (1) c2 = (10 m a ? cl2)/i inrush C (2) where cl1 and cl2 are the positive and negative output load capacitance. if the supply-tracking mode is enabled (track = high), during startup, the output with the slowest slew rate will also limit the slew rate of the opposite output (note: supply-tracking is also controlled by the resistive dividers on the fb pins. see supply tracking). additionally, c1 and c2 should be greater than 5nf to prevent large overshoot in the output voltage for transient loads with small capacitive loads. capacitor c3 and resistor r8 prevent q2 from momen- tarily turning on when the power pins first make contact. without c3, capacitor c2 and c gd(q2) would hold the gate of q2 near ground before the lt4220 could power up and pull the gate low. the minimum required value of c3 can be calculated by: c vv v cc ee th th gd q 3212 2 = - + ? ? (). () (3) where v th is the mosfets minimum gate threshold and v eemax is the maximum negative supply input voltage. if c2 is not used, the minimum value for c3 should be 10nf to ensure stability. c2 and c3 must be the same type to ensure tracking over temperature. +uvlo uvlo 12 3 4 5 6 v cc v ee on + on gate + v out + gate v out pwrgd 4220 f08 figure 8. typical timing sequence
13 lt4220 4220f applicatio s i for atio wu uu current limit/electronic circuit breaker the lt4220 features foldback current limit with an elec- tronic circuit breaker that protects against short-circuits or excessive supply currents. the current limit is set by placing sense resistors between v cc (pin 16) and sense + (pin 15) and between sensek (pin 2) and sense C (pin 3). an adjustable timer will trip an electronic circuit breaker if the part remains in current limit for too long. to prevent excessive power dissipation in the pass tran- sistors and to prevent voltage spikes on the input supply during overcurrent conditions at the output, the current folds back as a function of the output voltage, which is sensed at the feedback pins fb + and fb C . when the voltage at the fb + (or fb C ) pin is 0v, the sense amplifier offset is 15mv (C15mv), and limits the current to i limit = 15mv/ r s + (C15mv/r s C ). as the output voltage increases, the sense amplifier offset increases until the fb + (or fb C ) voltage reaches 0.85v (C0.75v), at which point the cur- rent limit reaches a maximum of i limit = 48mv/r s + (C 52mv/r s C ). timer function and autorestart the timer pin (pin 8) provides a method for setting the maximum time the lt4220 is allowed to operate in current limit. when the current limit circuitry is not active, the timer pin is pulled to gnd by a 3.3 m a current sink. whenever the current limit circuit becomes active, by either a positive or negative sense amplifier operating in current limit, a 65 m a pull-up current source is connected to the timer pin and the voltage rises with a slope equal to dv/dt = 65 m a/c timer . the desired current limit time (t) can be set with a capacitor value of: c timer = t ? 65 m a/1.24v (4) if the current limit circuit turns off, the timer pin will be discharged to gnd at a rate of: dv/dt = 3.3 m a/c timer (5) whenever the timer pin ramps up and reaches the 1.24v threshold, the internal fault latch is set and the fault pin (pin 11) is pulled low. gate + is pulled down to ground, gate C is pulled down to v ee , and the timer pin starts ramping back to gnd by the 3.3 m a current sink. after the fault latch is set, the lt4220 can be restarted by pulling the on + pin low after the timer pin falls below 0.5v. the lt4220 can also be restarted by cycling either supply beyond its uvlo. otherwise the part remains latched off. for autorestart, the fault pin can be tied to the on + pin. the autorestart will occur after the timer pin falls below 0.5v. undervoltage detection the on + and on C pins can be used to detect an undervoltage condition at the power supply inputs. the on + and on C pins are connected to analog comparators with 50mv of hysteresis. if the on + pin falls below its threshold voltage or the on C pin rises above its threshold voltage, the gate pins are pulled low and held low until the on + and on C pins exceed their turn-on thresholds (1.24v and C1.24v). ex- ternal capacitance at the on pins may be required to filter supply ringing from crossing the on comparator thresh- old. additionally there is an internal undervoltage lockout on both supplies of approximately v cc < 2.45v and v ee > C2.45v. if either supply is in uvlo, both gate pins will be pulled low and all internal latches will be reset. on C protection if the on C pin is driven directly and not connected to the negative supply through a resistor divider, a 10k resistor must be connected between the driver and the on C pin. power good detection the lt4220 includes two comparators for monitoring the output voltages. the fb + and the fb C pins are compared against 1.24v and C1.24v internal references respectively. the comparators exhibit 50mv of hysteresis. the com- parator outputs are wire-ored to the open collector pwrgd pin that is enabled once both gate + and gate C pins have reached their maximum gate drive voltage as indicated by the internal gate good latches. the pwrgd pin goes high impedance when both fb + and fb C inputs exceed v fb + h and v fb C h thresholds, gate + is fully on and gate C initially has been fully on.
14 lt4220 4220f applicatio s i for atio wu uu supply tracking if the track pin (pin 7) is high the supply power-up tracking mode is enabled. this feature forces both sup- plies to reach their final value at the same time, during power-up and for faults that drive the output supplies to zero. during this mode the gate pins are controlled to keep the differential magnitude of the fb pins to within 50mv. the fb pins are scaled versions of the output voltages. therefore, control of the fb pins, via the gate pins, will control the output voltages at the same scale. | d v fb(trk) | = |v fb + C v fb C | (6) supply tracking will continue until: either fb pin reaches the associated pwrgd threshold. if any fault condition occurs that turns the gate pins off, supply tracking will be reenabled. the gate off conditions include: (1) either on pin detects undervoltage, (2) internal undervoltage lock- out, (3) the fault latch is set by a current limit time-out. v ee bypassing the v ee supply pin should be filtered with an rc network to reduce high dv/dt slew rates from disturbing internal circuits. typical rc bypassing sufficient to prevent circuit misbehavior is r14 = 10 w and c5 = 1 m f. the gate C , sensek and sense C pins have been designed such that they can be pulled below or above v ee for short periods of time while the v ee pin is reaching its steady state voltage. if desired, a higher r14 ? c5 time constant may be used to prevent short circuit transients from tripping the v ee undervoltage lockout circuit at C2.45v. r14 should be sufficient to decouple c5 from causing transients on v inC during live insertion. under the condition of a short circuit on v out C , parasitic inductance and resistance in the v in C path will cause v in C to collapse toward 0v causing the v ee pin voltage to also discharge toward 0v before the external fet can be turned off (typically 7 m s to 10 m s). to prevent a uvlo condition from occurring, the r14 ? c5 time constant should be sufficient to hold the v ee pin voltage out of the v ee uvlo voltage range. if the v ee pin reaches its uvlo voltage, gate + will also be pulled low. for the case where c3 is large, causing an even slower n-channel fet turnoff, higher rc bypassing may be necessary to prevent tripping the v ee uvlo. on + , on C bypass capacitors bypass capacitors are required from on + to ground and on C to ground. a typical time constant is: tc (on + ) = (r1||r2)c7 = 44 m s tc (on C ) = (r3||r4)c8 = 44 m s supply ringing normal circuit design practice calls for capacitive bypass- ing of the input supply to active devices. the opposite is true for hot swap circuits that are connected into a backplane, where capacitive loading would cause tran- sients during an abrupt connection to the backplane. with little or no capacitive decoupling on the powered side of the n-channel fets, connection transients or load tran- sients will typically cause ringing on the supply leads due to parasitic inductance. it is recommended to use a snubber circuit comprising of a series 10 w and 0.1 m f capacitor to dampen transient ringing. the supply decoupling circuit on the v ee pin also provides a snubber for v in C . additionally, if the supply voltage overshoot can exceed the 22v maximum rating on the part, a transient voltage suppressor is recommended. voltage transients can oc- cur during load short-circuit conditions, where parasitic inductance in the supply leads can build up energy before the external n-channel fet can be turned off. this is especially true for the negative side fet where a large c3 value slows the turn off of the n-channel fet. subsequent overshoot when the fet is finally turned off can be as much as 2 the supply voltage even with the snubber circuit. additional protection using a transient suppressor may be needed to prevent exceeding the maximum supply voltage rating. supply reversal protection a variety of conditions on v out + and v out C may result in supply reversal. to protect devices connected to v out + and v out C protection diodes should be used. 1n4001 diodes can be used for most aplications. connection of these diodes (d1, d2) are shown in the front page typical application.
15 lt4220 4220f u package descriptio gn package 16-lead plastic ssop (narrow .150 inch) (reference ltc dwg # 05-08-1641) gn16 (ssop) 0502 12 3 4 5 6 7 8 .229 ?.244 (5.817 ?6.198) .150 ?.157** (3.810 ?3.988) 16 15 14 13 .189 ?.196* (4.801 ?4.978) 12 11 10 9 .016 ?.050 (0.406 ?1.270) .015 .004 (0.38 0.10) 45 0 ?8 typ .007 ?.0098 (0.178 ?0.249) .053 ?.068 (1.351 ?1.727) .008 ?.012 (0.203 ?0.305) .004 ?.0098 (0.102 ?0.249) .0250 (0.635) bsc .009 (0.229) ref .254 min recommended solder pad layout .150 ?.165 .0250 typ .0165 .0015 .045 .005 *dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side **dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side inches (millimeters) note: 1. controlling dimension: inches 2. dimensions are in 3. drawing not to scale information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
16 lt4220 4220f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear.com ? linear technology corporation 2003 lt/tp 0403 2k ? printed in usa related parts part number description comments ltc ? 1421 dual hot swap controller two circuit breakers for supplies from 3v to 12v and supports C12v ltc1422 single hot swap controller in so-8 operates from 3v to 12v ltc1645 dual hot swap controller operates from 1.2v to 12v, allows supply sequencing ltc1647 dual hot swap controller operates from 2.7v to 16.5v, separate on pins ltc4211 single hot swap controller with multifunction 2.5v to 16.5v, active inrush limiting, fast comparator current control ltc4230 triple hot swap controller with multifunction 1.7v to 16.5v, active inrush limiting, fast comparator current control v cc on + c6 1 f r2 r1 r4 r3 v ee v cc fault timer gnd track on pwrgd fb + r10 r9 v out + r12 r11 4220 f09 v out r7 10 fb sense + r s + r s gate + r6 1k r5 10 c1 10nf r8 1k c2 10nf c3 100nf q1 sub85n03-04 v ee sense sensek lt4220 gate q2 sub85n03-04 connect for auto restart backplane connector staggered pcb edge connector gnd must connect first *transient voltage suppressor gnd power good rpg 5.1k cl1 cl2 c7 c8 12 11 8 9 6 716 15 14 10 13 5 4 3 2 1 r14 10 r13 10 z2* z1* c5 1 f c4 100nf esd control + + u typical applicatio figure 9. hot swap controller on mainboard with tracking

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